Here, we will cover the fundamentals of integrated circuit (IC) prototyping, as well as silicon virtual prototypes (SVPs).
SVP Approaches Have Their Own Set of Issues
Modelling physical effects at a very high level of abstraction—during the rudimentary phase—will allow costly iterations to be terminated by an SVP. As these issues will be taken care of later in the flow, the end result is a quicker time to market. However, there are currently some SVP generation flows that can trigger their own unique set of errors. Back-end correlation issues may ensue, which will negate the very advantages of opting for an SVP to begin with.
Many conventional synthesis tools require large amounts of computational resources and take up too much time. Furthermore, the speed demands of modern prototyping are quite high, and many flows that are based on SPV technology will utilize a “dirty and fast” synthesis engine for prototyping purposes.
In addition, these synthesis tools are usually based on algorithms that are wholly antithetical to the primary engine, such as direct register-transfer level (RTL) mapping. In this instance, the ensuing gate-level netlist that is utilized to create the SVP isn’t an accurate portrayal of the original implementation of the design.
As such, once the SVP has been utilized to perform a timing analysis and exploration of the RTL, engineers will still be required to implement a full-up logic synthesis via a synthesis engine that is completely different. Furthermore, they need to do this so that they can generate the real netlist that will be passed on to the corporeal implementation. As can be seen by using the aforementioned SVP-based approach, the methodologies and the associated prototyping tools are dichotomous from the implementation tools as well as their associated methodologies.
There are many issues with this, such as a lack of correlation leading to an unpredictability in design convergence. Back-end to front-end iterations that are very time consuming will result via this approach. In sum, this actually defeats the purpose of using an SVP, as any benefits or advantages will be negated because of these issues.
A Cunning Approach to SVP
As can be seen, SVP has its own unique set of issues. The good news is that electronic design automation (EDA) companies are currently hard at work in order to find ways to bypass the issues that SVPs present. An example is Blast Prototype, which incorporates fixed timing concepts and gain-based synthesis. In this case, the corporeal implementation tools will work within the plane, and the fixed timing plane will actually be realized early in the process.
Magma’s Blast Prototype
All the timing optimization procedures are also implemented by the end of the synthesis step. Once the placement engine by Magma implements its task, a size-driven algorithm is utilized. The algorithm consists of cells that are all dynamically sized in order to adhere to their timing budgets: These timing budgets are actually based on the loads they see. Once placement is initialized, a routing engine that is load-driven is implemented in order to tune the spacing and width of the interconnection in order to ensure signal integrity as well as maintain the routing timing budgets.
Magma’s approach is exceptional because the computational effort and the amount of CPU memory needed to perform gain-based synthesis is actually a small fraction of what is required by standard synthesis tools. In other words, a synthesis engine that is gain-based can actually synthesize millions upon millions of gates simultaneously. In terms of Magma, the system can provide a ten-fold increase in capacity, vis-a-vis conventional synthesis solutions.
The Blast Create Component
Now, some designs may require as many as nine million gates. The good news is that Blast Create is one component of Blast Prototype. It takes a top-level floor plan, the SDC timing constraints, and RTL for the design—in either VHDL or Verilog—and outputs for an SVP. Blast Create actually incorporates the gain-based synthesis engine by Magma. As such, the SVP netlist that is actually generated by the system can be passed, as can the back-end implementation tools.
That is, there is no need to implement a separate logical synthesis step. In addition, the netlist can be routed to tools and another place if needed. By staying in the Magma flow, both the implementation environments and prototyping are based on the same methodologies, tools, and algorithms. The end result is any back-end to front-end iterations that are very time consuming are drastically reduced, and predictable design coverage, as well as high correlation, ensue.
Blast Create can also generate an SVP for very large designs in a singular pass. Its placement decisions are based on the concept of clusters, which allows it to have a high capacity. Groups of cells are automatically gathered into clusters via Blast Create, and each singular cluster can contain anywhere from ten to several hundred cells. As such, they are minute enough to preserve the placement quality, overall.
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